1. Field of the Invention
The present invention relates to a half tone image processing circuit which is used in an image processing section of a facsimile machine or the like for implementing half tone processing for scanned images which are to be digitized.
2. Prior Art
FIG. 1 is a block diagram showing a conventional half tone processing circuit and its associated image sensor. In the figure, 1 is an image sensor which reads a main scanning line of a document (will be termed "a line" hereinafter) and produces an analog image signal which represents the scanned image line, 2 is a picture signal sample/hold circuit which samples and holds the image signal and produces a picture signal in synchronism with a picture signal clock, 3 is a clock generation circuit which generates the picture signal clock, 4 is a dither generation circuit which produces elements of a dither matrix, 6 is a comparison circuit which compares the picture signal with elements of the dither matrix outputted by circuit 4 to convert the picture signal into a binary format, 7 is a scale reduction circuit which produces an canceled picture signal clock, 9 is a line feed pulse generation circuit which produces a line feed pulse in response to the reading of one line, 10 is a reset circuit which inhibits the operation of the dither generation circuit 4 and the scale reduction circuit 7, and 11 is a reduction control circuit which produces a scale reduction signal indicative of whether or not scale reduction is to be implemented. 12a indicates a binary picture signal, 12b indicates the picture signal clock produced by the scale reduction circuit 7, and 12c indicates the picture signal clock before cancellation of clock pulses by the circuit 7.
Next, the operation of this circuit will be explained. Initially, the image sensor 1 scans an image, one line at a time, and produces an analog signal the amplitude level of which represents the intensity of the image at each point along the line. Next, the picture signal sample/hold circuit 2 sample-holds the produced analog signal and generates a quantized picture signal in synchronism with the picture signal clock 12c.
The dither generation circuit 4 produces elements of a dither matrix in synchronism with the picture signal clock 12c. The following explanation is based on an example of a 4-by-4 dither matrix, which would be used in a half tone system of 16 shades or tones. The quantized picture signal is a multiple-tone signal which can be resolved into steps of 16 tones.
A multiple-tone image display using a dither matrix is based on the following principle. An image 101 is divided into a number of blocks each consisting of 16 (4.times.4) pixels as shown in FIG. 16. A dither matrix consisting of 16 (4.times.4) elements is prepared (see also FIG. 2 (d)). The pixels of each block are compared with the corresponding elements of the dither matrix, such that a pixel is judged to be black when the pixel level is lower than or equal to the element level, and is judged to be white when the pixel level is higher than the element level. It is assumed that the higher the pixel level, the lower the intensity. However, this is a matter of convention and the opposite designation may be used with no change in result. The pixel level to be compared with the dither matrix is in practice the level of the picture signal provided by the picture signal processing circuit 2.
The elements of the dither matrix are set to have values as shown in FIG. 2 (a), (b) and (c), for example. When a picture signal for an image portion with a 0% reflectivity (highest intensity) as shown in the leftmost section of FIG. 2 (a) is received, it is compared with the dither matrix, yielding binary signals 12a as shown in the rightmost section of FIG. 2 (a). Here, the binary signals may be such that black="1" and white="0", or vice versa. The picture signal produced by reading an image portion of 25% reflectivity yields a set of binary signals 12a including 25% white pixels as shown in the rightmost section of FIG. 2 (b). Similarly, a picture signal produced by reading an image portion of 50% reflectivity yields a set of binary signals 12a including 50% white pixels as shown in the rightmost section of FIG. 2 (c). The set of binary signals 12a corresponding to a block of 16 (4.times.4) pixels includes black pixels proportional to the intensity of the image, and therefore the 16 levels as a whole represent a grey scale or half tone system by analogy.
In the operation of the circuit arrangement shown in FIG. 1, the picture signal sample/hold circuit 2 produces a quantized picture signal, which is a half tone signal of 16 possible steps as described above, in synchronism with the picture signal clock 12c. The dither generation circuit 4 sequentially outputs elements of the dither matrix. The picture signal sample/hold circuit 2 delivers a picture signal consisting of 2048 pixels per line when a B4 size document is read by an image sensor. The dither generation circuit 4 is reset by the reset circuit 10 at the beginning of document scanning and sequentially generates elements of the dither matrix in accordance with the picture signal of the first line. After that, the circuit 4 receives line feed pulses from the line feed pulse generation circuit 9 and in response to these pulses produces dither matrix elements of picture signals of subsequent lines provided by the picture signal processing circuit 2. For example, the dither generation circuit 4 sequentially produces the dither elements of the first line in the order of A, B, C, D, A, B, C, D, A, B, and so on as shown in FIG. 3, (a). In response to the reception of a line feed pulse, the circuit 4 sequentially produces the dither elements of the second line in the order of E, F, G, H, E, F, G, H, E, F, and so on. In this manner, upon receiving a line feed pulse the circuit 4 is switched to produce dither elements for the next line. After the fourth line, dither elements of the first line are produced. In FIG. 16, a picture signal i-j is for a pixel on row i (line i) and in column j.
FIG. 4 is a block diagram showing an example of the dither generation circuit 4. The dither generation circuit 4 begins operation in response to the removal of the reset signal (see FIG. 5, (a)). The reset signal is turned off by the reset circuit 10 under control of a controller (not shown). A quaternary (0 to 3) counter 42 for producing a dither in the main scanning direction counts the picture signal clock pulses 12c (see FIG. 5, (b)) and outputs a binary signal 00, 01, 10 and 11 sequentially for each clock pulse. The count value produced by the counter 42 is decoded by a decoder 43 and thereafter fed to the column address input of matrix register 41, which outputs dither elements of the matrix from the column indicated by the decoded value from decoder 43. Register 41 may be a ROM, RAM or any other suitable addressable memory storage device. The row of the dither matrix is specified by the output of the decoder 45. A quaternary counter 44 for producing a dither in the secondary scanning direction counts the line feed pulses (see FIG. 5, (c)). The count value of the counter 44 is decoded by a decoder 45 and thereafter fed to the row address input of dither matrix register 41 for selecting a row of the dither matrix. In this manner, the dither matrix register 41 outputs the dither elements as shown in FIG. 5, (d). The comparison circuit 6 compares the picture signal samples with the dither elements and outputs the comparison result as the binary signal 12a.
A facsimile machine or a so-called "smart" copier may have an image scale reduction function. For example, it may scan a B4 sized text and send the image by reducing the size to A4. A scale reduction technique in this case is to cancel pixels or "thin out" the binary signal 12a at a certain interval. FIG. 6 shows an example of a scale reduction circuit 7 which cancels one bit out of every 6 bits in the main scanning direction and cancels one line out of every 6 lines in the secondary scanning direction, indicated in FIG. 3 (b). The circuit 7 starts operation in response to the removal of the reset signal and reception of an active (high) scale reduction signal provided by the reduction control circuit 11 (see FIG. 7, (a) and (b)). A hexal (0 to 5) counter 71 for determining the position of cancellation for each line counts the picture signal clock pulses 12c. The count value is delivered to a logical product (AND) gate 73 by way of an inverter 72. The AND gate 73 produces a high output when the count value from counter 71 is 5 (101 binary), otherwise it produces a low output. Consequently, at the output of a logical sum (OR) gate 78, every sixth pulse of the picture signal clock 12c is blocked or canceled in the output signal 12b, and is thus not transmitted to the image processing circuit. FIG. 7 (f) is an enlargement of area P in FIG. 7 (e). Another hexal counter 75 for determining an entire line to be canceled counts the line feed pulses and the count value is fed to an inverter 76 and to an AND gate 77, the output of which is as shown in FIG. 7 (d). This output is delivered to the OR gate 78, which then produces a high output during a period when the counter 75 has a count value of 5 (101 binary). Consequently, the picture signal clock 12c has all its pulses blocked from the image processing circuit 14 for every sixth scanning line.
In this manner, the picture signal clock 12c is subjected to pulse cancellation or inhibition for every one out of six pulses and every one out of six lines. The inhibition of the picture signal clock 12c results in the corresponding cancellation of bits of the binary signal 12a at the following stage of the half-tone image processing circuit 14. Accordingly, the image is reduced to 5/6 the original size. When the scale reduction signal from control circuit 11 is low, the 0R gate 78 is in a through state since counters 71 and 75 are disabled, causing the picture signal clock 12c to pass through the gate 78 unperturbed.
When scale reduction is not implemented, processing of the binary signal 12a in accordance with the picture signal clock 12b outputted by scale reduction circuit 7 results in a pattern as shown in FIG. 3 (b). In contrast, when scale reduction is utilized, the binary signal 12a processed in accordance with the picture signal clock 12b is as shown in FIG. 3 (d). This is because the dither matrix elements for the cancelled pixels continue to be outputted by the dither generation circuit 4 in response to clock signal 12c, as shown in FIG. 3(c). That is, as FIG. 1 make apparent, the dither generation circuit 4 continues to respond to clock signal 12c regardless of the operation of scale reduction circuit 7. FIG. 3 is based on the assumption that the pixels of image signals are all at the eighth level (50% reflectivity) of the 16 half tone steps. Numbers in parentheses in FIG. 3 (d) indicate the line numbers before cancellation. As seen from FIG. 3 (d), the image is deteriorated through the cancellation between bit 5 and bit 7 in the main scanning direction and between line 5 and line 7 in the secondary scanning direction, resulting in an uneven pixel pattern in the printed image, causing a deterioration in image quality.
In the conventional half tone processing circuit arranged as described above, scale reduction by pixel cancellation results in the discontinuity of a pixel pattern on both sides of an canceled pixel, and as a result the binary signal after cancellation reproduces an image of degraded quality.